Company Name

Larsen & Toubro ( Bangalore )

Job Description

• • HSIO PHY IP level test case porting to SoC level.
  • HSIO PHY SoC level Test case development, Running regression in RTL/GLS & Timing simulations.
  • HSIO PHY Virtual tester simulations in RTL/GLS & Timing simulations.
  • Hands-on experience in System Verilog, OVM/UVM based constrained random verification.
  • Experience with scripting languages like Python, Perl, skill, tcl or equivalent to automate flows is a plus.
  • Hands on Testbench bring up, integrating third party VIPs, digital design, verification, debugging, and waveform debug.
  • Knowledge on USB2/USB3/PCIE/UFS/MIPI/DDR PHY's functionality & Loopback tests concepts.
  • Knowledge on SoC level Interface/Configurability of HSIO PHY Registers.
  • Knowledge on HSIO PHY Controller and PHY + controller test case porting knowledge.
  • Generate of EVCD/Bench collaterals for target test cases.

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